Solid-state image sensor, method for producing solid-state image sensor, and electronic device

ABSTRACT

To provide a solid-state image sensor in which two or more semiconductor chips are bonded together without voids occurring in their bonding surfaces despite the conductive films bonded together at a high areal ratio. The solid-state image sensor includes at least a first semiconductor chip carrying thereon one or more than one of a first conductor and a pixel array, and a second semiconductor chip which bonds to the first semiconductor chip and carries thereon one or more than one of a second conductor and a logic circuit, with the first semiconductor chip and the second semiconductor chip bonding together in such a way that the first conductor and the second conductor overlap with each other and are electrically connected to each other, and the bonding occurring such that the first conductor and the second conductor differ from each other in the area of their bonding surfaces.

TECHNICAL FIELD

The present technology relates to a solid-state image sensor, a methodfor producing a solid-state image sensor, and an electronic device. Moreparticularly, the present technology relates to a technology of thesolid-state image sensor which includes a plurality of semiconductorchips bonded together.

BACKGROUND ART

The recent increasing popularization of digital cameras has stimulatedan active demand for the solid-state image sensor as the key part of thedigital camera. The solid-state image sensor is technically improving inperformance to meet requirements for high image quality and multiplefunctionality.

Similarly, there is an increasing spread of portable terminals, such ascellular phones, PDA (Personal Digital Assistant), note PC (PersonalComputer), and note tablets, which have the imaging function. This hasprovoked people to make such portable terminals easier to carry by sizereduction, weight reduction, and thickness reduction of the solid-stateimage sensor and components thereof. Another effort is being made tospread such portable terminals by cost reduction for the solid-stateimage sensor and components thereof.

In general, for example, the solid-state image sensor like CMOS(Complementary Metal Oxide Semiconductor) image sensor includes asilicon substrate and such components as photoelectric converters,amplifier circuits, and multilayered wiring layers, which are formed onthe receiving surface of the silicon substrate. These components arecovered with color filters and on-chip microlenses, and the receivingsurface has a cover glass bonded thereto with a spacer. Opposite thereceiving surface are formed terminals.

The foregoing solid-state image sensor has a signal processing circuitconnected thereto which performs a prescribed process on the signals tobe output. There is an increasing demand on processes to be performed bythe signal processing circuit as a result of the solid-state imagesensor having diversified functions.

Various attempts have been made to miniaturize the image sensorincluding a plurality of semiconductor chips connected together. Forexample, one of them is based on the SiP (System in Package) technologywhich is designed to seal a plurality of semiconductor chips in onepackage. This technology makes it possible to reduce the mounting area,thereby miniaturizing the entire structure. However, the SiP technologyhas a disadvantage that the wiring to connect the semiconductor chipstogether results in an extended transmission distance, which would bedetrimental to high-speed operation.

In the meantime, there is disclosed in PTL 1, for example, a solid-stateimage sensor which includes a first semiconductor substrate having thepixel region (pixel array) and a second semiconductor substrate havingthe logic circuit, which are bonded together. This constitution permitshigh-speed signal transmission. The solid-state image sensor is producedby sticking to each other a first semiconductor chip and a secondsemiconductor chip, both in half-finished state, with the former havingthe pixel array and the latter having the logic circuit, andsubsequently connecting the pixel array to the logic circuit, after thefirst semiconductor chip has been thinned down. This connection is madewith three interconnections, with the first one being conductorsconnected to the wiring of the first semiconductor chip, the second onebeing the through-type conductors which penetrate the firstsemiconductor chip and connect to the wiring of the second semiconductorchip, and the third one being the connecting wiring which connects thetwo interconnections to each other. The foregoing step for connection isfollowed by the step of making the two semiconductor chips into onecomplete semiconductor chip, which functions as a solid-state imagesensor of a back-illuminated type.

Moreover, there has been proposed in PTL 2 an idea for improvement overthe foregoing solid-state image sensor which includes the first andsecond semiconductor chips bonded together. According to this idea, inthe solid-state image sensor, the two semiconductor chips are notelectrically connected through the through-type conductor but connectedthrough the copper (Cu) electrodes protruding from the surfaces of thetwo semiconductor chips as a new technology.

In addition, there is disclosed in PTL 3 another solid-state imagesensor which employs the copper (Cu) electrode as the light-shieldinglayer. This light-shielding layer shuts out light emanating from the hotcarriers of the transistors in the logic circuit, thereby suppressingthe light incidence on the pixel array side. The disclosure claims thatthe semiconductor chip completed after bonding has a reduced thicknessas a whole.

CITATION LIST Patent Literature [PTL 1]

JP 2012-64709A

[PTL 2]

JP 2013-73988A

[PTL 3]

JP 2012-164870A

SUMMARY Technical Problems

The idea disclosed in PTL 3 mentioned above has a disadvantage that thecopper electrode to be used as the light-shielding layer has to have acoverage (or areal ratio) equal to or larger than a certain limit.

However, any attempt to meet the requirement for increasing the arealratio equal to or larger than a certain limit ends up with the formationof voids or regions where incomplete bonding occurs between the firstand second semiconductor wafers. In addition, such voids lack bondstrength, which brings about peeling in the step (following waferbonding) of thinning the silicon substrate of the first semiconductorwafer.

It is presumed that the unbonded region occurs because the Bonding-Wavespeed becomes uneven at the time of Wafer-To-Wafer Bonding as the resultof increasing the areal ratio of the copper electrode. This gives riseto regions (or voids) where bonding takes place relatively slow in theperipheral part of the wafer.

The present technology was completed in view of the foregoing. Thus, itis an object of the present technology to provide a solid-state imagesensor in which two or more semiconductor chips are bonded togetherwithout voids occurring in their bonding surfaces despite the conductivefilms bonded together at a high areal ratio.

Solution to Problems

Thus, the present technology discloses a solid-state image sensor whichincludes at least a first semiconductor chip carrying thereon one ormore than one of a first conductor and a pixel array, and a secondsemiconductor chip which bonds to the first semiconductor chip andcarries thereon one or more than one of a second conductor and a logiccircuit, in which the first semiconductor chip and the secondsemiconductor chip are bonded together in such a way that the firstconductor and the second conductor overlap with each other and areelectrically connected to each other, and the bonding occurs such thatthe first conductor and the second conductor differ from each other inarea of their bonding surfaces.

The present technology also discloses a method for producing asolid-state image sensor, the method including a step of preparing afirst semiconductor chip which has a first conductor and a pixel arrayformed thereon in singular or plural number, a step of preparing asecond semiconductor chip which has a second conductor and a logiccircuit formed thereon in singular or plural number, and a step ofplacing the first conductor formed on the first semiconductor chip andthe second conductor formed on the second semiconductor chip one overthe other for electrical connection, in which the first semiconductorchip and the second semiconductor chip are bonded to each other in sucha way that the first conductor and the second conductor differ from eachother in area of their bonding surfaces.

The present technology further discloses an electronic device whichincludes a solid-state image sensor including at least a firstsemiconductor chip carrying thereon one or more than one of a firstconductor and a pixel array, and a second semiconductor chip which bondsto the first semiconductor chip and carries thereon one or more than oneof a second conductor and a logic circuit; the first semiconductor chipand the second semiconductor chip being bonded together in such a waythat the first conductor and the second conductor overlap with eachother and are electrically connected to each other; the bondingoccurring such that the first conductor and the second conductor differfrom each other in area of their bonding surfaces.

Advantageous Effect of Invention

The solid-state image sensor disclosed herein includes two or moresemiconductor chips which are bonded together in such a way that theirconductive films are bonded to each other with a high areal ratio in thebonding surface. The wafer bonding in this manner suppresses the voidoccurrence. The effect of the present technology is not restricted tothe effect mentioned above; the effect may be variously modified asdescribed hereinafter.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram depicting an example of constitution of asolid-state image sensor pertaining to the present technology.

FIG. 2A is a schematic diagram depicting a laminate structure of thesolid-state image sensor pertaining to the present technology.

FIG. 2B is a schematic diagram depicting the laminate structure of thesolid-state image sensor pertaining to the present technology.

FIG. 2C is a schematic diagram depicting the laminate structure of thesolid-state image sensor pertaining to the present technology.

FIG. 3 is a schematic diagram depicting important parts of a solid-stateimage sensor according to a first embodiment of the present technology.

FIG. 4 is an enlarged view depicting important parts of a firstsemiconductor chip according to the first embodiment.

FIG. 5 is an enlarged view depicting important parts of a secondsemiconductor chip according to the first embodiment.

FIG. 6 is an enlarged view depicting important parts of a bonding partaccording to the first embodiment.

FIG. 7A is a diagram depicting a structure of a light-shielding partaccording to the first embodiment.

FIG. 7B is a diagram depicting the structure of the light-shielding partaccording to the first embodiment.

FIG. 7C is a diagram depicting the structure of the light-shielding partaccording to the first embodiment.

FIG. 8 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 1).

FIG. 9 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 2).

FIG. 10 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 3).

FIG. 11 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 4).

FIG. 12 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 5).

FIG. 13 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 6).

FIG. 14 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 7).

FIG. 15 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 8).

FIG. 16 is a diagram depicting an example of the process for producingthe solid-state image sensor according to the first embodiment (Part 9).

FIG. 17 is a schematic diagram depicting important parts of asolid-state image sensor according to a second embodiment of the presenttechnology.

FIG. 18 is a schematic diagram depicting important parts of asolid-state image sensor according to a third embodiment of the presenttechnology.

FIG. 19 is a schematic diagram depicting important parts of asolid-state image sensor according to a fourth embodiment of the presenttechnology.

FIG. 20A is a diagram depicting how to constitute a light-shieldinglayer in the solid-state image sensor according to the first embodimentof the present technology.

FIG. 20B is a diagram depicting how to constitute a light-shieldinglayer in a solid-state image sensor according to a fifth embodiment ofthe present technology.

FIG. 20C is a diagram depicting how to constitute the light-shieldinglayer in the solid-state image sensor according to the fifth embodimentof the present technology.

FIG. 20D is a diagram depicting how to constitute the light-shieldinglayer in the solid-state image sensor according to the fifth embodimentof the present technology.

FIG. 21 is an enlarged view depicting a layout of signal lines in apixel array according to the fifth embodiment.

FIG. 22A is a diagram illustrating a layout of a shield layer accordingto the fifth embodiment.

FIG. 22B is a diagram illustrating the layout of the shield layeraccording to the fifth embodiment.

FIG. 22C is a diagram illustrating the layout of the shield layeraccording to the fifth embodiment.

FIG. 23 is a schematic diagram illustrating constitution of anelectronic device according to a sixth embodiment of the presenttechnology.

DESCRIPTION OF EMBODIMENTS

The best modes for carrying out the present technology will be describedbelow with reference to the accompanying drawings. Incidentally, theembodiments explained below are typical embodiments and are not intendedto restrict the scope of the present technology. The descriptionproceeds in the following order.

1. Example of constitution of solid-state image sensor2. Example of laminate structure of solid-state image sensor3. Solid-state image sensor according to first embodiment4. Solid-state image sensor according to second embodiment5. Solid-state image sensor according to third embodiment6. Solid-state image sensor according to fourth embodiment7. Solid-state image sensor according to fifth embodiment8. Electronic device according to sixth embodiment

<1. Example of Constitution of Solid-State Image Sensor>

FIG. 1 is a block diagram depicting the example of the constitution ofthe solid-state image sensor pertaining to the present technology.

As depicted in FIG. 1, for example, a solid-state image sensor 1 isconstructed as a CMOS (Complementary Metal Oxide Semiconductor) imagesensor. The solid-state image sensor 1 includes a semiconductorsubstrate, for example, Si substrate (not depicted), a pixel region(pixel array) 3 on which a plurality of pixels 2 are regularly arrangedto form the two-dimensional array, and a peripheral circuit.

The pixel 2 has a photoelectric converter (for example, photodiode) anda plurality of pixel transistors (MOS transistors). The pixel transistormay include three transistors (for example, a transfer transistor, areset transistor, and an amplifying transistor). The pixel transistormay also include four transistors (including an additional selectivetransistor). Incidentally, the unit pixel has a similar equivalentcircuit to the well-known equivalent circuit and hence its detaileddescription is omitted.

In addition, the pixel 2 may be a single unit pixel or that of sharedpixel structure. The latter includes a plurality of photodiodes andshared transistors except transfer transistors and floating diffusion.In other words, in the case of pixel of shared structure, the pluralityof unit pixels include a photodiode and a transfer transistor sharingeach of other pixel transistors.

The peripheral circuit includes a vertical drive circuit 4, a columnsignal processing circuit 5, a horizontal drive circuit 6, an outputcircuit 7, and a control circuit 8.

The vertical drive circuit 4 includes shift resisters, for example. Thevertical drive circuit 4 selects the pixel drive wires and supplies thepixel drive wires with pulses to drive the pixels, thereby driving thepixels in the units of column. In other words, the vertical drivecircuit 4 performs selective scans sequentially in the verticaldirection in the units of pixel 2 of the pixel array 3. The verticaldrive circuit 4 also supplies the column signal processing circuit 5through vertical signal lines 9 with the pixel signals based on thesignal charges which have been generated by the photoelectric converterin response to the amount of light received by the photoelectricconverter of each pixel 2.

The column signal processing circuit 5 is arranged for each column ofthe pixels 2, for example. The column signal processing circuit 5performs signal processing, such as noise removal, for each column ofpixels on the signals output from the pixels 2 constituting one row.Specifically, the column signal processing circuit 5 performs signalprocessing such as CDS (Correlated Double Sampling) to remove fixedpattern noise inherent in the pixels 2, signal amplification, and A/D(Analog/Digital) conversion. The column signal processing circuit 5 alsohas the output stage which connects to a horizontal signal line 10through a horizontal selection switch (not depicted).

The horizontal drive circuit 6 includes shift registers, for example.The horizontal drive circuit 6 sequentially outputs horizontal scanningpulses, thereby selecting the column signal processing circuits 5 inorder, and causes the column signal processing circuits 5 to outputpixel signals to the horizontal signal line 10.

The output circuit 7 performs signal processing on signals which aresequentially supplied through the horizontal signal line 10 from each ofthe column signal processing circuits 5, and finally outputs the resultsof processing. The output circuit 7 sometimes performs buffering only orsometimes performs black level adjustment, correction of variation incolumns, and digital signal processing, for example.

The control circuit 8 accepts input clock and data to instruct theoperational mode and outputs such data as information inside thesolid-state image sensor 1. The control circuit 8 also generates theclock signal and control signal, according to the vertical sync signals,horizontal sync signals, and master clock, as the reference foroperation of the vertical drive circuit 4, the column signal processingcircuit 5, and the horizontal drive circuit 6. Moreover, the controlcircuit 8 inputs these signals into the vertical drive circuit 4, thecolumn signal processing circuit 5, and the horizontal drive circuit 6.

Input/output terminals 12 exchange signals with the outside.

<2. Example of Laminate Structure of Solid-State Image Sensor>

FIGS. 2A, 2B, and 2C are schematic diagrams depicting the laminatestructure of the solid-state image sensor pertaining to the presenttechnology. They will be referenced to describe the laminate structureof the solid-state image sensor pertaining to the present technology.

A solid-state image sensor 1 a as the first example is depicted in FIG.2A. The solid-state image sensor 1 a includes a first semiconductorsubstrate 21 and a second semiconductor substrate 22. The firstsemiconductor substrate 21 carries thereon a pixel array 23 and acontrol circuit 24, and the second semiconductor substrate 22 carriesthereon a logic circuit 25 including a signal processing circuit. Thefirst semiconductor substrate 21 and the second semiconductor substrate22 are electrically connected to each other so that they constitute thesolid-state image sensor 1 a in the form of a single semiconductor chip.

A solid-state image sensor 1 b as the second example is depicted in FIG.2B. The solid-state image sensor 1 b includes a first semiconductorsubstrate 21 and a second semiconductor substrate 22. The firstsemiconductor substrate 21 carries thereon a pixel array 23, and thesecond semiconductor substrate 22 carries thereon a control circuit 24and a logic circuit 25 including a signal processing circuit. The firstsemiconductor substrate 21 and the second semiconductor substrate 22 areelectrically connected to each other so that they constitute thesolid-state image sensor 1 b in the form of a single semiconductor chip.

A solid-state image sensor 1 c as the third example is depicted in FIG.2C. The solid-state image sensor 1 c includes a first semiconductorsubstrate 21 and a second semiconductor substrate 22. The firstsemiconductor substrate 21 carries thereon a pixel array 23 and acontrol circuit 24-1 to control the pixel array 23, and the secondsemiconductor substrate 22 carries thereon a logic circuit 25 includinga signal processing circuit and a control circuit 24-2 to control thelogic circuit 25. The first semiconductor substrate 21 and the secondsemiconductor substrate 22 are electrically connected to each other sothat they constitute the solid-state image sensor 1 c in the form of asingle semiconductor chip.

A CMOS solid-state image sensor may also include two or moresemiconductor chips bonded together, although this is not depicted. Forexample, the CMOS solid-state image sensor in the form of a single chipmay be formed by supplementing the foregoing first and secondsemiconductor chips with another semiconductor chip carrying thereon amemory element array, still another semiconductor chip carrying thereonadditional circuit elements, or the like. In other words, the resultingCMOS solid-state image sensor includes three or more semiconductor chipsbonded together.

<3. Solid-State Image Sensor According to First Embodiment>

[Constitution of Solid-State Image Sensor]

There is depicted in FIG. 3 the solid-state image sensor according tothe present technology, or the CMOS solid-state image sensor of aback-illuminated type according to a first embodiment. The CMOSsolid-state image sensor of the back-illuminated type is superior tothat of a front-illuminated type in sensitivity and noise level becauseit has the light receiver arranged on the circuit. The solid-state imagesensor 31 according to the first embodiment is similar to thesolid-state image sensor 1 a depicted in FIG. 2A in that it is based ona laminated semiconductor chip 32 which includes a first semiconductorchip 26 (including the pixel array 23 and the control circuit 24) and asecond semiconductor chip 28 (including the logic circuit 25) which arebonded together. The first and second semiconductor chips 26 and 28 arebonded together in such a way that their multilayered wiring layers faceeach other and their connecting wires are directly bonded to each other.

The first semiconductor chip 26 includes a first semiconductor substrate33 of silicon which has been thinned and a pixel array 34 formedthereon. The pixel array 34 includes a plurality of pixels arranged in atwo-dimensional pattern, with each pixel including a photodiode PD as aphotoelectric converter and a plurality of pixel transistors Tr1 andTr2. In addition, the semiconductor substrate 33 carries a plurality ofMOS transistors constituting the control circuit 24 formed thereon,although this is not depicted. The semiconductor substrate 33 has amultilayered wiring layer 37 formed on a surface 33 a thereof, with aninterlayer insulating film 53 interposed between them. The multilayeredwiring layer 37 includes wirings 35 (35 a to 35 d) and 36 of metal M1 toM5 in five layers. The wirings 35 and 36 are formed using copper (Cu) bythe dual damascene method. On the back side of the semiconductorsubstrate 33 is formed a light-shielding film 39 (including an opticalblack region 41), with an insulating film 38 interposed thereunder. Thesemiconductor substrate 33 additionally has a color filter 44 and anon-chip lens 45 which are formed on an effective pixel array 42, with aplanarized film 43 interposed thereunder. The on-chip lens 45 may alsobe formed on the optical black region 41.

The pixel transistors Tr1 and Tr2 depicted in FIG. 3 represent aplurality of pixel transistors. FIG. 3 schematically depicts some pixelsof the pixel array 34, and FIG. 4 depicts the detail of one pixel. Thefirst semiconductor chip 26 has a photodiode PD formed in the thinnedsemiconductor substrate 33. The photodiode PD includes, for example, ann-type semiconductor region 46 and a P-type semiconductor region 47close to the surface of the substrate. On the surface of the substratecarrying the pixel are formed the P-type semiconductor region 48, with agate insulating film interposed thereunder, and the pixel transistorsTr1 and Tr2, each including a gate electrode 48 and a pairedsource-drain region 49. The pixel transistor Tr1 adjacent to thephotodiode PD is equivalent to a floating diffusion FD. Individual unitpixels are separated from one another by an element separating region51. The element separating region 51 has, for example, an STI (ShallowTrench Isolation) structure, which is formed by embedding an insulatingfilm (such as SiO₂ film) in a groove formed in the substrate.

The first semiconductor chip 26 has the multilayered wiring layer 37 inwhich a conductive via 52 helps connection between the pixel transistorand the wiring 35 and between the adjacent upper and lower wirings 35.In addition, the connecting wiring 36 of metal M5 as the fifth layer isformed on a bonding surface 40 between the first semiconductor chip 26and the second semiconductor chip 28. The connecting wiring 36 isconnected to the wiring 35 d of metal M4 as the fourth layer through theconductive via 52.

The second semiconductor chip 28 has a logic circuit 55 constituting theperipheral circuit formed in the region which functions as thesemiconductor chip in a second semiconductor substrate 54 of silicon.The logic circuit 55 includes a plurality of MOS transistors Tr11 toTr14 including CMOS transistors. The second semiconductor substrate 54(depicted in FIG. 5) has in that portion close to the surface thereof amultilayered wiring layer 59 including wirings 57 [57 a to 57 c] and 58of metal M11 to M14 in four layers in this example, with an interlayerinsulating film 56 interposed thereunder. The wirings 57 and 58 areformed using copper (Cu) by the dual damascene method.

In FIG. 3, the MOS transistors in the logic circuit 55 are representedby the MOS transistors Tr11 to Tr14. Although the MOS transistors Tr11to Tr14 are schematically depicted in FIG. 3, the detailed structure ofthe MOS transistors Tr11 and Tr12 is, for example, depicted in FIG. 5.The second semiconductor chip 28 has the MOS transistors Tr11 and Tr12formed in the semiconductor well region on the surface of the secondsemiconductor substrate 54, such that each transistor includes a pairedsource-drain region 61 and a gate electrode 62, with a gate insulatingfilm interposed between them. The MOS transistors Tr11 and Tr12 areseparated from each other by an element separating region 63 of the STIstructure, for example.

The second semiconductor chip 28 has the multilayered wiring layers 59in which a conductive via 64 makes a connection between each of the MOStransistors Tr11 to Tr14 and each of the wirings 57 and between each ofthe adjacent upper and lower layers and each of the wirings 57. It alsohas the connecting wiring 58 of metal M14 as the fourth layer, whichfaces the bonding surface 40 between the first semiconductor chip 26 andthe second semiconductor chip 28. The connecting wiring 58 is connectedto the appropriate wiring 57 c of metal M13 as the third layer throughthe conductive via 64.

The first semiconductor chip 26 and the second semiconductor chip 28 areelectrically connected together in such a way that their multilayeredwiring layers 37 and 59 face each other and the connecting wirings 36and 58 (which face the bonding surface 40) are bonded together directly.An interlayer insulating film 66 near the bonding part includes twoinsulating films combined together, one being an insulating film capableof blocking the copper diffusion from the copper wiring and the otherbeing an insulating film incapable of blocking the copper diffusion fromthe copper wiring. The fabrication method will be given later. Theconnecting wirings 36 and 58 are bonded together directly through thecopper wiring by the heat diffusion method. The interlayer insulatingfilms 66 (except for the connecting wirings 36 and 58) are bondedtogether by means of plasma or adhesive.

In addition to the direct bonding between the connecting wirings 36 and58 that face the bonding surface 40, there is another way of bonding bymeans of plasma after forming an extremely thin uniform insulating thinfilm 900 on the surface of the multilayered wiring layers 37 and 59.Incidentally, the insulating thin film 900 is not depicted in FIG. 3.

Moreover, according to the present embodiment, the first semiconductorchip 26 and the second semiconductor chip 28 are bonded together, with alight-shielding layer 68 inserted between them, which is a conductivefilm of the same kind as the connecting wiring, as depicted in FIGS. 3and 6 (which are enlarged views of important parts). In other words,according to the present embodiment, the light-shielding layer 68includes a first conductive material 71 and a second conductive material72, with the former functioning as a light-shielding part includingmetal M5 which is identical with the connecting wiring 36 in the firstsemiconductor chip 26, and the latter functioning as a light-shieldingpart including metal M14 which is identical with the connecting wiring58 in the second semiconductor chip 28.

The solid-state image sensor according to the present embodiment has thelight-shielding part constructed as depicted in FIGS. 7A to 7C. Thelight-shielding part 71 according to the present embodiment depicted inFIG. 7A (top view) includes stripes arranged in the horizontal directionand separated by openings 73 at a certain pitch. Although thelight-shielding part 71 is wider than the opening 73 according to thepresent embodiment, the opening 73 may be wider than the light-shieldingpart 71.

The light-shielding parts 72 according to the present embodimentdepicted in FIG. 7B are arranged horizontally in a stripy pattern at acertain pitch so that they are separated by openings 74. According tothe present embodiment, the light-shielding parts 72, which are narrowerthan the opening 73, are so arranged as to cover the openings 73 for thelight-shielding part 71.

The light-shielding layer 68 which is formed after the light-shieldingparts 71 and 72 have been bonded together is depicted in FIG. 7C (topview). It is noted that the light-shielding parts 71 and 72 overlap oneanother to close the openings. In other words, the region in which thefirst conductor of the light-shielding part 71 and the second conductorof the light-shielding part 72 are formed is equal to or larger than theregion in which the pixel array 23 is formed. Incidentally, according tothe present embodiment, the light-shielding part 71 is wider than thelight-shielding part 72, but the light-shielding part 72 may be widerthan the light-shielding part 71. The region of the bonding surface 40in which the conductors of the light-shielding parts 71 and 72 areformed may partly have openings.

The light-shielding part 71 and the light-shielding part 72 which coversthe opening 73 between the adjacent light-shielding parts 71 are formedsuch that they partly overlap. The light-shielding parts 71 and 72 aredirectly bonded together at their overlapping region when the connectingwirings 36 and 58 are directly bonded together. One of thelight-shielding parts 71 and 72 constitutes the wiring having theopening 73 and the other covers the opening 73 (or it has a larger areathan the opening 73) and is so formed as to partly overlap. The opening73 may take on any other shape than the horizontal strip depicted inFIG. 7A.

The light-shielding layer 68 should preferably be kept potentiallystable with a fixed grounding voltage, for example. This can be achievedby voltage application to the first semiconductor substrate 33 or thesecond semiconductor substrate 54 or both.

[Method for Producing Solid-State Image Sensor]

The solid-state image sensor 31 according to the first embodiment isproduced by the method illustrated in FIGS. 8 to 16. FIGS. 8 to 10depict the processes of producing the first semiconductor chip havingthe pixel array. FIGS. 11 to 13 depict the processes of producing thesecond semiconductor chip having the logic circuit. FIGS. 14 to 16depict the processes that follow the process for bonding.

As depicted in FIG. 8, the process starts with fabricating the firstsemiconductor wafer 33 of silicon, for example (to be referred to as asemiconductor substrate hereinafter) so as to form a semiconductor wellregion 30, which will be covered by each semiconductor chip later. Next,the semiconductor well region 30 is given the photodiodes PD whichfunction as the photoelectric converter for each pixel. Incidentally,the element separating region 51 (depicted in FIG. 4) may be formedbeforehand (not depicted in FIG. 8). The photodiodes PD are so formed asto extend in the depth direction of the semiconductor well region 30.The photodiodes PD are formed in the effective pixel array 42 and theoptical black region 41, which all together constitute the pixel array34.

In the next process, the semiconductor well region 30 has its surface 33a fabricated so that a plurality of pixel transistors, which constituteeach pixel, are formed thereon. The pixel transistor includes, forexample, transfer transistor, reset transistor, amplifying transistor,and selective transistor. Here, they are represented by the pixeltransistors Tr1 and Tr2 as mentioned above. Each of the pixeltransistors Tr1 and Tr2 includes the paired source-drain region and thegate electrode, with the gate insulating film interposed thereunder.

The semiconductor substrate 33 has its upper surface 33 a provided witha plurality of wiring layers together with the conductive via 52 throughthe interlayer insulating film 53. In this embodiment, the wiring layersinclude the wirings 35 [35 a, 35 b, 35 c, 35 d] of metal M1 to M4 infour layers in this example. The wiring 35 may be formed by the dualdamascene method. The foregoing process includes forming the connectinghole and wiring groove simultaneously in the interlayer insulating film53 by the via first method, forming the metal film capable of blockingcopper diffusion and the copper seed film, and embedding the copperlayer by the plating method. The metal film capable of blocking copperdiffusion may be formed using any one of Ta, TaN, Ti, TiN, W, WN, Ru,TiZrN, or alloy thereof, for example. The foregoing process is followedby CMP (Chemical Mechanical Polishing) to remove excess copper layer andform the copper wiring integral with the planarized conductive via.Subsequently, an insulating film capable of blocking copper diffusion isformed (not depicted). The insulating film capable of blocking copperdiffusion may be formed using any one of SiN, SiC, siCN, SiON, etc. Theforegoing processes are repeated to form the wirings 35 a to 35 d ofmetal M1 to M4 in four layers.

The subsequent process (depicted in FIG. 9) includes sequentiallyforming a first insulating film 76 incapable of blocking copperdiffusion, a second insulating film 77 incapable of blocking copperdiffusion, and an insulating film 75 capable of blocking copperdiffusion. The first and second insulating films 76 and 77 are formedusing SiO2 film, SiCOH film, or the like. The insulating film 75 capableof blocking copper diffusion may be the similar insulating film of SiN,SiC, SiCN, SiON, or the like as mentioned above, for example. Theinsulating film 75 capable of blocking copper diffusion, the firstinsulating film 76, and the second insulating film 77 constitute part ofthe interlayer insulating film 53. The next process is to performpatterning on the insulating film 75 capable of blocking copperdiffusion (on the uppermost surface), the second insulating film 77, andthe first insulating film 76 by lithography and etching for the viafirst method, thereby forming a via hole 80 selectively. Then, thesecond insulating film 77 undergoes patterning so that an opening 78 isformed selectively. In other words, patterning is performed so as toform the opening 78 corresponding to the light-shielding part 71(excluding the opening 73), an opening 79 corresponding to theconnecting wiring 36 to be formed, and the via hole 80.

The subsequent process (depicted in FIG. 10) includes filling theopenings 78 and 79 and the via hole 80 with copper by the dual damascenemethod (in the similar way as mentioned above), thereby forming thelight-shielding part 71 having the opening 73, the conductive via 52connecting to the wiring 35 d, and the connecting wiring 36. Thelight-shielding part 71 and the connecting wiring 36 are formed by metalM5 as the fifth layer. This process forms the multilayered wiring layer37 including the wirings 35 a to 35 d of metal M1 to M5, the connectingwiring 36, the light-shielding part 71, the interlayer insulating film53, and the insulating films 75 to 77. In this stage, it is desirablethat the wiring 35 d 1 of metal M4 (as the fourth layer) connecting tothe connecting wiring 36 should sufficiently extend toward and overlapwith the light-shielding part 71 so that the light emanating from thelogic circuit does not leak to the photodiode PD.

In addition, the extremely thin uniform insulating thin film 900 isformed on the light-shielding part 71 and the connecting wiring 36.

On the other hand, the second semiconductor wafer (referred to assemiconductor substrate hereinafter) 54 of silicon, for example, has asemiconductor well region 50 formed for each of the individualsemiconductor chips, as depicted in FIG. 11. The semiconductor wellregion 50 has the logic circuit 55 including a plurality of MOStransistors Tr11 to Tr14, which are merely representative as mentionedabove. Although not depicted, the element separating region 63 (see FIG.5) may be formed beforehand.

The semiconductor substrate 54 is given on the upper surface thereof thewirings 57 [57 a, 57 b, 57 c] of metal M11 to M13 in three layers inthis example, including the conductive via 64, which are formed throughthe interlayer insulating film 56. The wiring 57 may be formed by thedual damascene method as follows. First, the interlayer insulating filmhas the connecting hole and wiring groove formed simultaneously thereinby the via first method. Then, it has the metal film capable of blockingcopper diffusion and the copper seed film formed therein and itsubsequently has the copper layer formed therein by plating. The metalfilm capable of blocking copper diffusion may be formed using any of Ta,TaN, Ti, TiN, W, WN, Ru, TiZrN, and alloy thereof, for example. Thisprocess is followed by CMP (Chemical Mechanical Polishing) to removeexcess copper layer. This gives the copper wiring integral with theplanarized conductive via. The subsequent process forms the insulatingfilm capable of blocking copper diffusion (not depicted). Thisinsulating film capable of blocking copper diffusion may be formed usingany of SiN, SiC, siCN, SiON, etc. The foregoing processes are repeatedto form the wirings 57 a to 57 c of metal M11 to M13 in three layers.

The subsequent step (depicted in FIG. 12) includes sequentially forminga first insulating film 82 incapable of blocking copper diffusion, asecond insulating film 83 incapable of blocking copper diffusion, and aninsulating film 81 capable of blocking copper diffusion. The first andsecond insulating films 82 and 83 are formed using SiO2 film, SiCOHfilm, or the like. The insulating film 81 capable of blocking copperdiffusion may be the similar insulating film of SiN, SiC, SiCN, SiON, orthe like as mentioned above, for example. The insulating film 81 capableof blocking copper diffusion, the first insulating film 82, and thesecond insulating film 83 constitute part of the interlayer insulatingfilm. The next process is to perform patterning on the insulating film81 capable of blocking copper diffusion (on the uppermost surface), thesecond insulating film 83, and the first insulating film 82 bylithography and etching for the via first method, thereby forming a viahole 86 selectively. Then, the second insulating film 83 undergoespatterning so that openings 84 and 85 are formed selectively. Theopening 84 is formed at the position where it covers the light-shieldingpart 71 and the opening 73 in the first semiconductor chip. The opening84 should preferably be so formed as to cover the opening 73 of thelight-shielding part 71 and partly overlaps the light-shielding part 71so that there will not be light leakage due to misalignment when thefirst and second semiconductor substrates are bonded together later. Inother words, patterning is performed so that it has the opening 84corresponding to the light-shielding part 72 to be formed, the opening85 corresponding to the connecting wiring 58 to be formed, and the viahole 86.

The subsequent process (depicted in FIG. 13) is to form the openings 84and 85 and fill the via hole 86 with copper by the dual damascenemethod, thereby forming the light-shielding part 72, the conductive via64 connecting to the wiring 57 c, and the connecting wiring 58, in thesimilar way as mentioned above. The light-shielding part 72 and theconnecting wiring 58 are formed by metal M14 as the fourth layer. Inthis way there is formed the multilayered wiring layer 59 including thewirings 57 a to 57 c of metal M11 to M13, the connecting wiring 58, thelight-shielding part 72, the interlayer insulating film 56, and theinsulating films 81 to 83.

Moreover, an extremely thin uniform insulating thin film 901 is formedon the light-shielding part 72 and the connecting wiring 58.

The next process (depicted in FIG. 14) is to bond together the firstsemiconductor substrate 33 and the second semiconductor substrate 54 insuch a way that multilayered wiring layers of the first semiconductorsubstrate 33 and the second semiconductor substrate 54 face each otherand their connecting wirings 36 and 58 come into direct contact witheach other for electrical connection. In other words, this processcauses the first and second semiconductor substrates 33 and 54 to bephysically bonded together and electrically connected to each other.This process also causes the light-shielding parts 71 and 72 to bedirectly bonded together at their overlapping parts. That is, thebonding between the connecting wirings 36 and 58 and between thelight-shielding parts 71 and 72 is accomplished by the heat diffusionmethod, which is performed at approximately 100° C. to 500° C. Theinsulating films (as the interlayer insulating films) are bondedtogether by means of plasma (after surface treatment) or adhesive.

As mentioned above, the bonding of the first conductor of thelight-shielding part 71 to the second conductor of the light-shieldingpart 72 is accomplished by inserting an insulating film between theirbonding surfaces 40 and then applying heat to promote the crystal growthof copper as the electrical conductor. This establishes the electricalconnection near the bonding surface 40. This causes the first conductorand the second conductor to be arranged nearer to the bonding surface 40than the wiring 35 and the logic circuit 55 which are formedrespectively on the first semiconductor chip 26 and the secondsemiconductor chip.

The next process (depicted in FIG. 15) is to grind and polish, by CMP orthe like, the back side of the first semiconductor substrate 33 forthickness reduction to such an extent that there remains a necessarythickness for the photodiode PD.

The next process (depicted in FIG. 16) is to coat the surface of thethinned semiconductor substrate with the light-shielding film 39, withthe insulating film 38 interposed thereunder, that covers that part ofthe photodiodes PD corresponding to the optical black region. Moreover,the photodiodes PD corresponding to the effective pixel array arecovered with the color filters 44 and the on-chip lenses 45, with theplanarized film 43 interposed thereunder.

The next process is to separate the first and second semiconductorsubstrates 33 and s54, which have been bonded together, into individualsemiconductor chips. Thus there is obtained the solid-state image sensor31 (depicted in FIG. 3) as desired.

It is desirable to make the light-shielding parts 71 and 72, theconnecting wirings 36 and 58, and the wirings of metal M5 and M14 at thesame level as them, from a material which is highly conductive, highlycapable of shielding light, and easy to bond. Such a material includesnot only copper but also any one of Al W, Ti, Ta, Mo, Ru, and alloythereof.

The light-shielding layer 68 (or the light-shielding parts 71 and 72 inthis example) should have an adequate thickness which is determinedaccording to the wavelength of light emanating from the secondsemiconductor chip 28. The present embodiment requires thelight-shielding layer 68 to block light originating from hot carriers inthe MOS transistor in the second semiconductor chip 28. Consequently,the light-shielding layer should be thick enough to block light having awavelength of approximately 1 μm. This means that the thickness of thelight-shielding layer 68 (or the light-shielding parts 71 and 72) shouldbe approximately 50 to 800 nm, for example.

The present embodiment that covers the solid-state image sensor 31 andthe method for production thereof requires that the first and secondsemiconductor chips 26 and 28 should be bonded together in such a waythat the light-shielding layer 68 and the shield layer againstelectrical noise are formed by only the first and second conductors 71and 72 in the neighborhood of the bonding surface 40 between the firstsemiconductor chip 26 and the second semiconductor chip 28. Moreover, inthe neighborhood of the bonding surface 40, the first conductor 71 andthe second conductor 72 come into contact with each other in such a waythat the area of the former in contact with the bonding surface 40 islarger than the area of the latter in contact with the bonding surface40. That is, the contact areas for the two are not equal. Consequently,according to the solid-state image sensor 31 and the method forproduction thereof described herein, it is possible to achieve the waferbonding, with two layers of conductive film connecting to each otherasymmetrically such that one has a larger contact area than the other.Bonding in this manner prevents voids from occurring at the bondingsurface 40. Moreover, the avoidance of void occurrence leads to thesolid-state image sensor 31 with improved image quality. The first andsecond conductors 71 and 72 may be bonded together satisfactorily solong as their areas at the bonding surface 40 are not equal. It ispermissible that the second conductor 72 has a larger bonding area thanthe first conductor 71.

The term “asymmetrically” means that the areal ratio of copper is equalto or less than 30% for the lower substrate and equal to or more than70% for the upper substrate, so that the resulting layout ensures 100%light shielding after bonding. The areal ratio of the higher substrateshould preferably be equal to or larger than 70%, more preferably equalto or larger than 87%, and the areal ratio of the lower substrate shouldpreferably be equal to or smaller than 30%, more preferably equal to orsmaller than 13%. Incidentally, the first and second conductors 71 and72 in the neighborhood of the bonding surface 40 may be replaced by adummy conductor.

The present embodiment that covers the solid-state image sensor 31 and amethod for production thereof requires that the first and secondsemiconductor chips 26 and 28 should be bonded together in such a waythat the light-shielding layer 68 is formed by metal M5 and M14 in thesame layer as the connecting wirings 36 and 58 near their bondingregion. This light-shielding layer 68 protects the pixel array in thefirst semiconductor chip 26 from the light emitted by the hot carriersof the MOS transistor of the logic circuit 55 in the secondsemiconductor chip 28. Suppression of the adverse effect due to lightemanating from hot carriers reduces dark current and random noise.

According to the present embodiment, the method for producing thesolid-state image sensor 31 involves the process of forming thelight-shielding layer 68 from metal M5 and M14 which are in the samelayers as the connecting wirings 36 and 58. This technology offers theadvantage of reducing the entire thickness of the bonded semiconductorchips and hence the solid-state image sensor 31 as a whole more than theone in the past. The result is the solid-state image sensor 31 with alow level of dark current and random noise which is realized withoutincrease in the total thickness of the semiconductor chip.

Moreover, according to the present embodiment, the method for producingthe solid-state image sensor 31 involves the step of forming thewirings, connecting wirings, and light-shielding layer at the same time.This reduces the number of producing processes and masking processes andthe cost of material. The result is the low-priced solid-state imagesensor with a low level of dark current and random noise.

<4. Solid-State Image Sensor According to Second Embodiment>

The following which refers to FIG. 17 describes the solid-state imagesensor according to a second embodiment of the present technology. Thesecond embodiment differs from the first embodiment (depicted in FIG.16) in that the connecting wiring 36 and the wiring 57 c of metal M13are connected to each other through the light-shielding part 72, withoutthe conductive via 64 being formed for the wiring layer 58 and thelight-shielding part 72. The solid-state image sensor 31 according tothe second embodiment produces the similar effect to that in thesolid-state image sensor 31 according to the first embodiment. Moreover,it offers the advantage in the reduction of producing processes andproduction cost which accrues from not forming the conductive via 64.

<5. Solid-State Image Sensor According to Third Embodiment>

The following which refers to FIG. 18 describes the solid-state imagesensor according to a third embodiment of the present technology. Thethird embodiment differs from the first embodiment (depicted in FIG. 16)in that a wiring 902 and a wiring 903 are bonded togetherasymmetrically, with the wiring 902 having a larger connecting area andthe wiring 903 having a smaller connecting area, like thelight-shielding layer 68, even in the case where the connecting wiring36 and the wiring 58 are used for power supply. The solid-state imagesensor 31 according to the third embodiment produces the similar effectto that in the solid-state image sensor 31 according to the firstembodiment. Moreover, it offers the advantage of suppressing voids whichare likely to occur at the time of bonding. This results from thewirings 902 and 903 differing in connecting area in addition to thelight-shielding layer 68.

<6. Solid-State Image Sensor According to Fourth Embodiment>

The following which refers to FIG. 19 describes the solid-state imagesensor according to a fourth embodiment of the present technology. Thefourth embodiment differs from the first embodiment (depicted in FIG.16) in that the second semiconductor chip 28 includes two layers of thesecond semiconductor substrate 54 which are laminated one over another.The interlayer insulating film and the second semiconductor substrate 54adjacent thereto have the wirings 57 c electrically connected to eachother through a wiring 904. The solid-state image sensor 31 according tothe fourth embodiment produces the similar effect to that in thesolid-state image sensor 31 according to the first embodiment.Incidentally, the solid-state image sensor according to the presenttechnology may include four or more layers of the semiconductorsubstrate, without being restricted to three or less layers.

<7. Solid-State Image Sensor According to Fifth Embodiment>

The following which refers to FIGS. 20 to 22 describes the solid-stateimage sensor according to a fifth embodiment of the present technology.The fifth embodiment differs from the first embodiment (depicted in FIG.16) in that the light-shielding layer 68 has not only the horizontalstripy pattern (depicted in FIG. 7) but also the slant stripy pattern orcheckered pattern (in plan view).

FIG. 20A depicts the light-shielding layer 68 which has a horizontalstripy pattern (in plan view) as in the first embodiment. Incidentally,the light-shielding parts 71 and 72 may be identical or different inwidth in their longitudinal direction. FIG. 20B depicts thelight-shielding layer 68 which has a slant stripy pattern (in plan view)extending from the upper left to the lower right. FIG. 20C depicts thelight-shielding layer 68 which has a checkered pattern (in plan view).The light-shielding layer 68 includes the light-shielding part 71 andthe light-shielding part 72 which overlap each other in such a way thateach of the rectangular areas in the latter covers each of therectangular openings 73 in the former, with the rectangular area havinga larger area than the rectangular opening 73. Incidentally,“rectangular” includes “square.” FIG. 20D depicts the light-shieldinglayer 68 having a slant checkered pattern which is formed by turning thecheckered pattern of FIG. 20C in the clockwise direction through acertain degree of angle.

The solid-state image sensor according to the present embodiment has thepixel array whose signal wire layout is depicted in FIG. 21 (enlargedview). According to the present embodiment, the pixel array 23 includesa plurality of photodiodes which are arranged in the horizontal andvertical directions. Moreover, the pixel array 23 has reset signal linesM21, transfer signal lines M22, and pixel selecting signal lines M23,which are arranged horizontally at a certain pitch. The pixel array 23also has the vertical signal lines M3, which are arranged vertically ata certain pitch.

The solid-state image sensor according to the present embodiment has theshield layer whose layout is depicted in FIGS. 22A to 22C.

The light-shielding layer (shield layer) 68 depicted in FIG. 22A (topview) includes the light-shielding parts 71 and 72 which are so arrangedas to form the vertical stripy pattern, with a plurality of openings 73and 74 left at a certain pitch. The vertical shielding layer like thisis liable to cause the vertical signal line M3 to fluctuate in its totalcapacity because of the difference that occurs between the verticalsignal line M3 and the shield layer 68.

The shield layer 68 depicted in FIG. 22B (top view) includes thelight-shielding parts 71 and 72 which are so arranged as to form thehorizontal stripy pattern, with a plurality of openings 73 and 74 leftat a certain pitch. The horizontal shield like this is liable to causethe horizontal signal lines M21 to M23 to fluctuate in their totalcapacity because of the difference that occurs between the horizontalcontrol lines M21 to M23 and the shield layer 68.

The shield layer 68 depicted in FIG. 22C (top view) includes thelight-shielding parts 71 and 72 which are so arranged as to form theslant stripy pattern, with a plurality of openings 73 left at a certainpitch from the upper left to the lower right. The slant shield like thiswill be free from fluctuation in the total capacity because theinterlayer capacity will be uniform between the vertical signal line M3and the shield layer 68 for each of the horizontal control lines M21 toM23. The result is lower band noise in the solid-state image sensor thanthat with the vertical or horizontal stripy pattern.

The result of arranging, as mentioned above, the shield layers 68 aslantin a stripy or checkered pattern at regular intervals with respect tothe horizontal signal lines M21 to M3 and the vertical signal line M3 ofthe logic circuit 55 makes the capacity uniform between the shield layer68 and each of the signal lines throughout the entire pixel array 23.The result is reduced electrical noise in the solid-state image sensor31. Moreover, the attempt to prevent reflection by arranging aslant theshield layer 68 in a stripy pattern which does not intersect at rightangles with all the signal lines will make the effect of capacitycoupling uniform.

<8. Electronic Device According to Sixth Embodiment>

The following is a description of the solid-state image sensor accordingto a sixth embodiment of the present technology, which is depicted inFIG. 23.

FIG. 23 is a diagram illustrating the electronic device according to thepresent technology. The electronic device according to the presenttechnology described above includes, for example, camera systems (suchas digital camera and video camera), portable telephones (with imagingfunction), and others (with imaging function), to which is applied thesolid-state image sensor according to the present technology.

FIG. 23 illustrates the sixth embodiment which demonstrates a camera asan example of the electronic device according to the present technology.The camera covered in the present embodiment is exemplified by a videocamera capable of taking static images or dynamic images. A camera 201according to the present embodiment includes a solid-state image sensor202, an optical system 203 to lead the incident light to thephotodetector of the solid-state image sensor 202, and a shutter 204. Italso includes a drive circuit 205 to drive the solid-state image sensor202 and a signal processing circuit 206 to process the output signalsfrom the solid-state image sensor 202.

The solid-state image sensor 202 may be selected from the solid-stateimage sensors pertaining to the foregoing embodiments. The opticalsystem (or optical lens) 203 focuses the incident light from the subjecton the sensitive surface of the solid-state image sensor 202. Thisprocess causes the solid-state image sensor 202 to accumulate signalcharges for a certain period of time. The optical system 203 may be anoptical lens including a plurality of optical lenses.

The shutter 204 controls the length of the period in which thesolid-state image sensor 202 is exposed to and shut off from theincident light. The drive circuit 205 transmits the drive signal tocontrol the solid-state image sensor 202 for its transmitting action andthe shutter 204 for its shutter action. The solid-state image sensor 202transmits signals in response to the drive signal (timing signal)received from the drive circuit 205. The signal processing circuit 206processes various signals. After having undergone signal processing, thevideo signals are stored in a storage medium (or memory) or dispatchedto the monitor.

Having the solid-state image sensor 202 of the back-illuminated typewhich is defined in the present technology, the electronic deviceaccording to the sixth embodiment makes the pixel array free from thelight emanating from the hot carriers of the MOS transistors in thelogic circuit, thereby suppressing dark current and random noise. Thisleads to the electronic device, such as camera, capable of producinghigh-quality photographs, for example.

The embodiments according to the present technology are not restrictedto the embodiments mentioned above; they may be modified in various wayswithin the scope of the present technology. More than one of theforgoing embodiments may be combined together or partly, for example.

The present technology may be embodied as follows.

(1) A solid-state image sensor including at least:

a first semiconductor chip carrying thereon one or more than one of afirst conductor and a pixel array; and

a second semiconductor chip which bonds to the first semiconductor chipand carries thereon one or more than one of a second conductor and alogic circuit,

in which the first semiconductor chip and the second semiconductor chipare bonded together in such a way that the first conductor and thesecond conductor overlap with each other and are electrically connectedto each other, and

the bonding occurs such that the first conductor and the secondconductor differ from each other in area of their bonding surfaces.

(2) The solid-state image sensor according to Paragraph (1), in whichthe bonding occurs such that the area of smaller bonding surface for theconductor accounts for equal to or more than 70% of the area of largerbonding surface for the conductor.

(3) The solid-state image sensor according to Paragraph (1), in whichthe bonding occurs such that the area of smaller bonding surface for theconductor accounts for equal to or more than 60% of the area of largerbonding surface for the conductor.

(4) The solid-state image sensor according to Paragraph (1), in whichthe region of the bonding surfaces in which the first conductor and thesecond conductor are formed is blocked by one of the first conductor andthe second conductor.

(5) The solid-state image sensor according to Paragraph (1), in whichthe region of the bonding surfaces in which the first conductor and thesecond conductor are formed has apertures at some parts.

(6) The solid-state image sensor according to Paragraph (1), in whichthe first semiconductor chip has a wiring and a connecting hole formedtherein to fix the potential of the first conductor and the secondconductor.

(7) The solid-state image sensor according to Paragraph (1), in whichthe second semiconductor chip has a wiring and a connecting hole formedtherein to fix the potential of the first conductor and the secondconductor.

(8) The solid-state image sensor according to Paragraph (1), in whichthe first conductor and the second conductor are each arranged closer tothe bonding surface than the logic circuit and a wiring which are formedon the first semiconductor chip and the second semiconductor chip.

(9) The solid-state image sensor according to Paragraph (1), in whichthe region in which the first conductor and the second conductor areformed is equal to or larger than the region in which the pixel array isformed.

(10) The solid-state image sensor according to Paragraph (1), in whichthe first conductor and the second conductor are formed in plural numbersuch that they are aslant to the direction of a signal line of an analogcircuit which is formed in the first semiconductor chip and the secondsemiconductor chip.

(11) A method for producing a solid-state image sensor, the methodincluding:

a step of preparing a first semiconductor chip which has a firstconductor and a pixel array formed thereon in singular or plural number;

a step of preparing a second semiconductor chip which has a secondconductor and a logic circuit formed thereon in singular or pluralnumber; and

a step of placing the first conductor formed on the first semiconductorchip and the second conductor formed on the second semiconductor chipone over the other for electrical connection,

in which the first semiconductor chip and the second semiconductor chipare bonded to each other in such a way that the first conductor and thesecond conductor differ from each other in area of their bondingsurfaces.

(12) An electronic device including:

a solid-state image sensor including at least

-   -   a first semiconductor chip carrying thereon one or more than one        of a first conductor and a pixel array, and    -   a second semiconductor chip which bonds to the first        semiconductor chip and carries thereon one or more than one of a        second conductor and a logic circuit;

the first semiconductor chip and the second semiconductor chip beingbonded together in such a way that the first conductor and the secondconductor overlap with each other and are electrically connected to eachother;

the bonding occurring such that the first conductor and the secondconductor differ from each other in area of their bonding surfaces.

REFERENCE SIGNS LIST

-   1, 1 a to 1 c, 31: Solid-state image sensor-   2: Pixel-   3, 23, 34: Pixel array (pixel region)-   4: Vertical drive circuit-   5: Column signal processing circuit-   6: Horizontal drive circuit-   7: Output circuit-   8, 24, 24-1, 24-2: Control circuit-   9: Vertical signal line-   10: Horizontal signal line-   21, 33: First semiconductor substrate-   22, 54: Second semiconductor substrate-   25, 55: Logic circuit-   26: First semiconductor chip-   28: Second semiconductor chip-   30, 50: Semiconductor well region-   32: Laminated semiconductor chip-   33 a: Surface-   35 a to 35 d, 36, 57 a to 57 c, 58, 902 to 904: Wirings-   37, 59: Multilayered wiring layer-   38: Insulating film-   39: Light-shielding film-   40: Bonding surface-   41: Optical black region-   42: Effective pixel array-   43: Planarized film-   44: Color filter-   45: On-chip lens-   47, 48: P-type semiconductor region-   49, 61: Source-drain region-   51, 63: Element-separating region-   52, 64: Conductive via-   53, 56, 66: Interlayer insulating film-   62: Gate electrode-   68: Light-shielding layer-   71: Light-shielding part (first conductor)-   72: Light-shielding part (second conductor)-   73, 74, 78, 79, 84, 85: Opening-   75, 81: Insulating film capable of blocking copper diffusion-   76, 82: First insulating film-   77, 83: Second insulating film-   80, 86: Via hole-   900, 901: Insulating thin film-   PD: Photodiode-   Tr1, Tr2: Pixel transistor-   M1 to M5, M13, M14: Metal-   FD: Floating diffusion-   Tr11 to Tr14: MOS transistor

What is claimed is:
 1. A solid-state image sensor comprising at least: afirst semiconductor chip carrying thereon one or more than one of afirst conductor and a pixel array; and a second semiconductor chip whichbonds to the first semiconductor chip and carries thereon one or morethan one of a second conductor and a logic circuit, wherein the firstsemiconductor chip and the second semiconductor chip are bonded togetherin such a way that the first conductor and the second conductor overlapwith each other and are electrically connected to each other, and thebonding occurs such that the first conductor and the second conductordiffer from each other in area of their bonding surfaces.
 2. Thesolid-state image sensor according to claim 1, wherein the bondingoccurs such that the area of smaller bonding surface for the conductoraccounts for equal to or more than 70% of the area of larger bondingsurface for the conductor.
 3. The solid-state image sensor according toclaim 1, wherein the bonding occurs such that the area of smallerbonding surface for the conductor accounts for equal to or more than 60%of the area of larger bonding surface for the conductor.
 4. Thesolid-state image sensor according to claim 1, wherein the region of thebonding surfaces in which the first conductor and the second conductorare formed is blocked by one of the first conductor and the secondconductor.
 5. The solid-state image sensor according to claim 1, whereinthe region of the bonding surfaces in which the first conductor and thesecond conductor are formed has apertures at some parts.
 6. Thesolid-state image sensor according to claim 1, wherein the firstsemiconductor chip has a wiring and a connecting hole formed therein tofix the potential of the first conductor and the second conductor. 7.The solid-state image sensor according to claim 1, wherein the secondsemiconductor chip has a wiring and a connecting hole formed therein tofix the potential of the first conductor and the second conductor. 8.The solid-state image sensor according to claim 1, wherein the firstconductor and the second conductor are each arranged closer to thebonding surface than the logic circuit and a wiring which are formed onthe first semiconductor chip and the second semiconductor chip.
 9. Thesolid-state image sensor according to claim 1, wherein the region inwhich the first conductor and the second conductor are formed is equalto or larger than the region in which the pixel array is formed.
 10. Thesolid-state image sensor according to claim 1, wherein the firstconductor and the second conductor are formed in plural number such thatthey are aslant to the direction of a signal line of an analog circuitwhich is formed in the first semiconductor chip and the secondsemiconductor chip.
 11. A method for producing a solid-state imagesensor, the method comprising: a step of preparing a first semiconductorchip which has a first conductor and a pixel array formed thereon insingular or plural number; a step of preparing a second semiconductorchip which has a second conductor and a logic circuit formed thereon insingular or plural number; and a step of placing the first conductorformed on the first semiconductor chip and the second conductor formedon the second semiconductor chip one over the other for electricalconnection, wherein the first semiconductor chip and the secondsemiconductor chip are bonded to each other in such a way that the firstconductor and the second conductor differ from each other in area oftheir bonding surfaces.
 12. An electronic device comprising: asolid-state image sensor including at least a first semiconductor chipcarrying thereon one or more than one of a first conductor and a pixelarray, and a second semiconductor chip which bonds to the firstsemiconductor chip and carries thereon one or more than one of a secondconductor and a logic circuit; the first semiconductor chip and thesecond semiconductor chip being bonded together in such a way that thefirst conductor and the second conductor overlap with each other and areelectrically connected to each other; the bonding occurring such thatthe first conductor and the second conductor differ from each other inarea of their bonding surfaces.